For example, in a NAND type flash memory device, a plurality of memory cell transistors are formed in an active region formed along a line direction in a semiconductor substrate, and strings each having a predetermined number of memory cell transistors, which are set to one set, are provided. A drain and a source which are located at both ends of the string are provided with a contact, and are provided with a selection gate transistor in order to cut off a current flowing through the contacts. The selection gate transistor on the drain side is a selection gate transistor STD, and the selection gate transistor on the source side is a selection gate transistor STS.
In the above-mentioned configuration, the contact of the selection gate transistor STD provided on the drain side is provided so as to come into contact with each of element formation regions corresponding to the strings. In addition, the contact of the selection gate transistor STS provided on the source side is provided so as to come into contact with the element formation regions of the plurality of strings in common. In this case, since the contact of the selection gate transistor STD on the drain side is formed for each of the strings, a contact plug is disposed which adopts a staggered disposition in which a plurality of contacts are shifted so that the adjacent contacts do not come into contact with each other. On the other hand, since the contact of the selection gate transistors STS on the source side comes into contact with the plurality of strings in common, a contact region is formed in a groove pattern to cross the element formation region.
For this reason, a density difference in processing is increased in forming a contact hole of the selection gate transistor STD on the drain side and forming a contact groove of the selection gate transistor STS on the source side. Therefore, between the contact hole on the drain side and the contact groove on the source side, a large difference in the amount of etching occurs in a layer located below the contact due to a loading effect of etching during contact processing. Accordingly, the depression of a shallow trench isolation (STI) film which is an element isolation insulating film between the element formation regions particularly becomes remarkable, and thus the contact and a diffusion layer in the element formation region approach each other in the contact groove on the source side which has a large digging amount due to the density difference, which results in the deterioration of junction leakage.
As a measure against the above-mentioned problem, for example, there is a process of connecting the element formation regions between STS and STS to thereby form a connected element formation region and removing the element isolation insulating film between the element formation regions by adding a resist covering process during the processing of the element formation region. However, this process has problems such as an increase in a chip cost due to the addition of the resist covering process and the fluctuation in a threshold value of STS which is caused by the diffusion of a dopant to the STS side due to an increase in the net amount of implantation into the diffusion layer by the connection between the element formation regions.